Coding standard MPEG enables storing the images of a digital image sequence in a reduced memory space, or transmitting these images in a channel of reduced flow. A coded image must be decoded before being able to be displayed, for example on a television screen.
FIG. 1 schematically shows in the form of blocks the main elements of a device 2 for decoding and displaying digital image sequences coded according to standard MPEG. This device includes a decoder (DECOD) 4 connected via a bus 6 to a memory (MEM) 8 in which the coded images to be decoded are stored. The images decoded by the decoder are temporarily stored in memory 8, before being provided to a screen (SCRN) 10 connected to bus 6 via a display control and management device (DIS) 12. The decoder and the display controller are controlled by a circuit such as a microprocessor (μP) 14 connected via a bus 7 to provide and receive control signals and data. Microprocessor 14 especially provides the decoder with orders for decoding the coded images stored in memory 8. Conventionally, to order the decoding of coded image stored in an area of memory 8, microprocessor 14 provides decoder 4 with the address of the beginning of this area, and with the image decoding order starting from a given time. The operation of such a circuit is well known by those skilled in the art and it will not be detailed any further.
Existing analog television systems conventionally provide displaying several images on screen upon a same screen scanning. This for example enables displaying one or several images incrusted in a main image and simultaneously visualizing several television channels. There is a need for a device for decoding images coded according to standard MPEG enabling such a simultaneous display, that is, enabling decoding of a plurality of images within a period of vertical scanning of a television screen.
The device of FIG. 1 enables decoding and displaying the images of a single image sequence. Thus, a solution consists of duplicating this device as many times as simultaneously decoded and displayed images are desired.
It is conventional in a television system to divide an image in two interlaced frames and to display each of the two frames upon two successive vertical screen scannings. According to standard MPEG, an image can be coded in three different ways: either in the form of a complete image including the two interlaced frames (“frame” image), or in the form of two half-images, each of which corresponds to one of the frames (“field” images), or else in the form of a non-interlaced complete image (“progressive” image). The following description only relates to interlaced images of both types, since progressive images can, in a known manner, be processed in the same way as the interlaced half-images. A same image sequence may be formed of images corresponding to both coding types. The different image sequences that are desired to be decoded and simultaneously displayed may also have different codings. The decoding of each type of coded image corresponds to a specific operation of decoder 4.
FIG. 2A illustrates the decoding of a sequence of two images I1 and I4, each coded in the form of two half-images I1T and I1B, and I4T and I4B respectively. The frame contained in each decoded half-image must be displayed in a period TVSYNC, and a half-image can thus be decoded in a period TVSYNC. Decoder 4 receives from microprocessor 14 the order to decode half-images I1T, I1B, I4T, I4B, respectively at times t100, t200, t300 and t400, each distant by a period TVSYNC. The respective decodings of half-images I1T, I1B, I4T, I4B occur in the period TVSYNC immediately following the decoding order. It should be noted that, to ensure a proper operation of the decoding and display device, it is desirable for the decoding of a half-image to be no longer than a maximum duration equal to one period TVSYNC and not to continue in the following period.
FIG. 2B illustrates the decoding of a sequence of two images I2 and I5 coded in the form of complete images. The two frames included in a complete decoded images must be displayed during two consecutive periods TVSYNC, and a complete image can be decoded in two periods TVSYNC. Decoder 4 receives from microprocessor 14 the order to decode complete images I2 and I5 respectively at times t100 and t300. The respective decodings of images I2 and I5 occur during the two successive periods TVSYNC that immediately follow the decoding order. In this case also, to ensure a proper operation, it is desirable for the decoding not to be continued after the end of the maximum duration, here of two periods, which is assigned thereto. It should be noted that memory 8 is a buffer that only contains a few images of a sequence, which are written and read in phase with the reception of the sequence by the decoding and display device. When several image sequences coming from different sources are considered, it is possible for these sequences not to be in phase, in terms of periods TVSYNC, and for them to have to be decoded and displayed with this phase shift. Especially, two image sequences coded in the form of complete images may be shifted by one screen scanning period TVSYNC.
FIG. 2C illustrates the decoding of a sequence formed of two images I3 and I6 coded in the form of complete images, the decoding order of which is given to decoder 4 with a phase shift of one period TVSYNC with respect to the sequence of FIG. 2B. The order to decode images I3 and I6 is given to the decoder at times t200 and t400, and their respective decodings occur during the two successive periods TVSYNC that immediately follow the decoding order.
Considering a circuit enabling simultaneous decoding and display of three image sequences such as those of the preceding drawings, which uses three distinct devices such as that in FIG. 1, each of these devices can decode with its own phase the image sequence provided thereto. Such a circuit operates satisfactorily, but has several disadvantages. In particular, it uses three MPEG decoders, which are large, bulky and expensive circuits.